職位描述 The candidate is expected to be responsible ffollowing tasks:- Participate in complex Chip DFT/DFD feature architecture definition- Implement DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic- Generate DFT related timing constraints work ftiming closure- Develop verify high coverage cost effective test patterns fthe production test- Design, implement verify other DFX (debug, characterization, yield etc) feature- Evaluate establish the advanced DFT/DFD tools flow as DFT CAD 職位要求 7+ years fBachel5+ years fmaster degree experience in DFT design verification, test pattern development KEY KNOWLEDGE, SKILLS ABILITIES REQUIRED- Good Knowledge of Scan/ATPG, MBIST boundary scan other DFT techniques- Good Knowledge of industry DFT tools like DFTMax, TetraMax ,TestKompress, FastScan, Tessent Mbist, SMS etc- Good knowledge of digital SoC/ASIC design, including STA, verification RTL coding- Proficient in hardware description languages such as Verilog, System Verilog VHDL- Good Knowledge of script language, such as Tcl, Python, Perl DFT platform development skill is good plus fDFT CAD function- Good English hearing, speaking, reading writing capabilities- Strong commitment to schedule work quality, good team player